In a superscalar computing apparatus using a reservation technique for handling data dependencies, a reorder buffer is commonly used to keep track of dispatched instructions and retired instructions in appropriate order. One major function of such a reorder buffer is to check the instruction operands during decoding for possible matches between dispatched read operands and destination operands of previous instructions in the reorder buffer. If such a match is detected, then a tag identifying the matched destination operand will be sent along with the read operand of the dispatched instruction to the reservation station. By means of such tag, the reservation station may check the results bus from the functional units for data returning to the reorder buffer and on detection of the appropriate tag, can directly receive the result for immediate processing.
The reorder buffer commonly has a write pointer which identifies the first instruction in the pipe line within the reorder buffer, and a read pointer which points to the entry after the last instruction in the pipeline. Reorder buffers are commonly loop first-in-first-out (FIFO) registers which if full or empty result in the read and write pointer pointing to the same entry. Such data processing requirements are necessary for a superscalar computing apparatus employing a pipelined instruction processing technique. Typically in such a computing apparatus a fetch-batch of a plurality of instructions is processed during each cycle. A design goal for such apparata is to dispatch and execute multiple instructions per cycle, but impediments to reaching that design goal are encountered in the event of data dependencies among instructions or branch instructions.
An instruction dependent upon data to be calculated by a different instruction cannot begin its operation until its required operands are available. If an operand is calculated by a previous instruction, then the second instruction must wait until the previous instruction has completed execution; thus, data dependencies among instructions can delay execution of instructions and degrade operation of the computing apparatus. Branch instructions may also degrade operation of the computing apparatus since such instructions often must wait for a condition to be known before executing. Both of these problems (data dependencies and branch instructions) may result in halting the flow of instructions within a superscalar system employing a pipeline instruction processing technique. The flow of instructions may also be disrupted by "interrupts" and "traps". Interrupts and traps are words reserved for extraordinary causes of stopping the normal execution of the instruction stream. Interrupts and traps can be occasioned by external pins that are user-asserted, illegal instructions, preset traces, stopping points, memory errors or other causes. The processor must store the current conditions, processor states, and the address of the current instruction to service a trap or interrupt (another sequence of instructions). After completion of the trap/interrupt routine, the processor must return to normal execution of the instruction stream. Interrupts and traps can be imprecise in their occurrences, and the reorder buffer must keep track of the instruction stream for proper stopping and restarting of normal instruction execution.
The present invention provides an apparatus and method for resolving such data dependencies and other interruptions among a plurality of instructions within a storage device such as a reorder buffer. The present invention is particularly useful in a superscalar computing apparatus employing pipeline instruction processing.